Liquid crystal displays (LCDs) are widely used flat panel display devices. As is well known to those having skill in the art, an LCD generally includes two spaced apart substrates with liquid crystals therebetween. A plurality of spaced apart gate lines are formed on a substrate, and a plurality of spaced apart data lines are formed on the substrate that intersect the plurality of spaced apart gate lines. Accordingly, the gate lines and data lines define an array of pixels. An array of pixel electrodes is provided, a respective one of which is in a respective one of the pixels. An array of thin film transistors is also provided, each comprising a gate electrode that is connected to one of the spaced apart gate lines, a gate insulator on the gate electrode, and an amorphous silicon layer on the gate insulator. Spaced apart source and drain electrodes are provided on the amorphous silicon layer. The source electrode is connected to one of the spaced apart data lines. The drain electrode overlaps a pixel electrode, and is electrically connected thereto through a contact hole therebetween.
FIG. 1 is a schematic diagram of a pixel of a conventional LCD. It will be understood that these pixels replicate in an array to form an LCD. As shown, a plurality of spaced apart gate lines 30 and a plurality of spaced apart data lines 40 are formed on a substrate and define an array of pixels. A pixel electrode 160, for example an indium tin oxide electrode, is included in a pixel. As shown in FIG. 1, the pixel electrode 160 may also partially overlap a gate line 30. A thin film transistor (TFT) 20 is located at the upper right corner of the pixel below the pixel to which it is connected. However, other positions may be used.
The TFT 20 includes a drain electrode which is connected to the pixel electrode 160, a gate electrode 142 which is connected to the gate line 30 and source electrode 144 which is connected to the data line 40. The pixel electrode 160 and the drain electrode 140 are generally formed in different layers of the LCD and are separated from each other by a passivation layer. The drain electrode 140 overlaps the pixel electrode 160 and is electrically connected thereto through a contact hole 10 therebetween in the passivation layer. As is well known, the contact hole 10 may be formed by etching the passivation layer to expose a portion of the drain electrode 140.
An LCD displays desired images by controlling the brightness of each pixel. The brightness of a pixel is controlled by the gate line 30, the data line 40, the TFT 20 and the pixel electrode 160. In general, a data signal is first sent through the data line 40, and a gate signal is sent to the selected gate line 30. The gate electrode 142 of the TFT 20 receives the gate signal and turns on the TFT 20 so that the data signal can pass from the source electrode 144 to the drain electrode 140, through an amorphous silicon layer 120, and then to the pixel electrode 160. Upon receiving the data signal, the pixel electrode 160 controls the amount of light passing through the pixel based on the data signal received, thereby controlling the brightness of the pixel.
FIG. 2 is an enlarged view of FIG. 1 at the pixel contact hole 10. Outlines of the amorphous silicon layer 120, the drain electrode 140, and the pixel electrode 160 are shown in FIG. 2.
FIG. 3 is a cross-sectional view of FIG. 2 taken along the section line III-III'. A gate insulator 110 is provided on an LCD substrate such as a glass substrate 100. The amorphous silicon layer 120 is provided on the gate insulator 110 extending from adjacent the pixel contact hole 10 to the TFT 20.
A doped amorphous silicon layer 130, generally doped with donor impurities and referred to as n+a-Si, is provided on the amorphous silicon layer 120. Its edges extend short of an edge of the amorphous silicon layer 120 near the pixel hole contact and creates a first conventional profile section 170 shown in FIG. 3.
The drain electrode 140 is located on the doped amorphous silicon layer 130. An edge of the drain electrode also extends short of an edge of the amorphous silicon layer 120 near the pixel hole contact 10. The drain electrode 140 partially covers the doped amorphous silicon layer 130. However, at least one of its edges is aligned with an edge of the doped amorphous silicon layer 130 and creates the first conventional profile section 170 on the amorphous silicon layer 130. The first conventional profile section 170 may be created by an etching process that etches portions of the doped amorphous silicon layer 130 that are not covered by the drain electrode 140.
In addition to the doped amorphous silicon layer 130 and the drain electrode 140, a portion of the amorphous silicon layer 120 also contributes to the first conventional profile section 170. In particular, a portion of the amorphous silicon layer 120 may be inadvertently etched in the etching process, since the amorphous silicon layer 120 has similar etching properties to the doped amorphous silicon layer 130. Therefore, the first conventional profile section 170 is relatively high, and has a steep slope, since the heights of the drain electrode 140, the doped amorphous silicon 130 and the etched out portion of the amorphous silicon layer 120 all contribute to the profile section.
As shown in FIG. 3, the first conventional profile section 170 exists on the amorphous silicon layer 120 where edges of the drain electrode 140 extend short of edges of the amorphous silicon layer 120. Thus, the pixel contact hole 10 is almost complete surrounded by the first conventional profile section 170.
Returning to the description of the array structure, a passivation layer 150 completely covers the drain electrode 140 and the first conventional profile section 170. A portion of the passivation layer 150 is removed to form the pixel contact hole 10. The pixel electrode 160 is then formed on the passivation layer, contacting the drain electrode 140 through the pixel contact hole 10. The pixel electrode 160 receives the data signal for appropriately aligning liquid crystals in a pixel to display images, through the pixel contact hole 10 and via the drain electrode.
As can be seen in FIGS. 2 and 3, the pixel electrode 160 extends the furthest adjacent the pixel contact hole 10, compared to the amorphous silicon layer 120, the doped amorphous silicon layer 130, and the drain electrode 140. The pixel electrode 160 covers the portion of the passivation layer 150 on the first conventional profile section 170. Thus, the pixel electrode 160 also has a second conventional profile section 180 which has relatively large step height due to the height of the first conventional profile section 170.
As a result, an open pixel electrode may occur on the second conventional profile section 180 during pixel electrode patterning due to its height and the steep slope. The open pixel electrode produces a defect that may prevent proper processing of the data signal by the pixel electrode 160, which can result in poor display quality.